Re: 440GX MMU

On Mon, Dec 06, 2004 at 12:39:49PM -0600, Kumar Gala wrote:

The TS provides an additional bit of address space on Book-E processors 
(440, e500, etc).  An exception automatically clears the MSR[IS, DS] 
fields which are used to compare against the TLB's TS field.

It was the case at one point in time (may still be) that on 440, the 
interrupt context was TS = 0, everything else was TS = 1.  Matt was 
going to (or may have) changed it so everything is TS = 0 so we could 
save a few TLB entries.

It's changed in 2.6 (all AS=0), in 2.4 I never got around to finishing
the update to the MMU handling. Since then, 2.6 has gone way beyond
2.4 in features/fixes so I don't intend to do anything more with
2.4. Patches are welcome for linuxppc-2.4, though.

-Matt