On Sat, 2004-01-17 at 03:29, Muhammad Sarwar wrote:

This problem was discussed on mailing list before also and you can eliminate this problem by inserting a sync instruction at a certain place in the 8260 interrupt handling code. See, for example, http://www.geocrawler.com/archives/3/8358/2002/11/100/10173445/

Add a __asm__ volatile("sync"); at the end of the m8260_mask_and_ack  function in arch/ppc/kernel/ppc8260_pic.c to fix it.

The code looks like crap... do we have any guarantee that those accesses
are done in order and did read the controller ?

I'd rather add eieios and read back the value to enforce ordering...

Ben.


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