Re: Any restrictions on DMA address boundry?

On Thu, Sep 25, 2003 at 01:25:00PM -0700, Eugene Surovegin wrote:

At 12:56 PM 9/25/2003, Matt Porter wrote:

quoted

When a buffer is allocated using the allowed methods (as defined in
DMA-mapping.txt) to obtain memory for use in DMA, there is
no guarantee that the buffer is cacheline aligned.

Hmm, I don't think this is true.

DMA-mapping.txt explicitly states that pci_alloc_consistent() returns
aligned memory buffer:

" ... The cpu return address and the DMA bus master address are both
guaranteed to be aligned to the smallest PAGE_SIZE order which
is greater than or equal to the requested size.  This invariant
exists (for example) to guarantee that if you allocate a chunk
which is smaller than or equal to 64 kilobytes, the extent of the
buffer you receive will not cross a 64K boundary..."

I think it's safe to assume that PAGE_SIZE alignment also guarantees
cacheline alignment for all existing CPUs.

Yes, that's correct.  However, I was alluding to kmalloc()'ed
buffers that are to be used with the streaming calls in the
DMA API.

-Matt

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