Hi Everyone,


	Patrick,

	I can give you what I have our SCCR and PLPRCR registers set to.
However I cannot guaranty it will work for your board.

Our board's SCCR is set to 0x2260000H
This corresponse to setting
COM = 01 to set clock output to half strength
TBS = 1  to set Timebase freq source to GCLK2 divided by 16
RTDIV = 0 clock is divided by 4
RTSEL = 0  OSCM is selected
CRQEN = 1 System switches to high speed clk durring CPM activity
PRQEN = 1 System switches Normal high on interrupt
EBDF = 00 CLKOUT is GCLK2 divided by 1
DFSYNC = 0 SYNCCLK divded by 1
DFBRG = 00 BRGCLK divide by 1
DFNL = 000 divide clk by 2
DFNH = 000 divide clk by 1

RES = 0 all reserved bits set to 0

in binary
RES |COM | RES | TBS | RTDIV | RTSEL | CRQEN | PRQEN | RES | EBDF | RES | DFSYNC |
DFBRG | DFNL | DFNH | RES
0   | 01 | 000 | 1   | 0     | 0     | 1     | 1     | 00  | 00   | 00  | 00     |
00    | 000  | 000  | 00000



Our board's PLPRCR is set to 0x0090X000 in Normal High Mode
This corresponse to setting
MF = 000000001001  multiply OSCCLK by 10
SPLSS, TEXPS, and TMIST are represented by X because they are status bits
CSRC = 0  sys clk generated by DFNH
LPM = 00 Normal High Mode
CSR = 0 No reset on checkstop
LOLRE = 0  No reset on Loss Of lock
FIOPD = 0  No pulldown on address and data busss during sleep

When put into Doze Low Mode it changes to 0X00900500
CSRC = 1 sys clock generated by DFNL
LPM = 01 Doze high/low mode




Patrick Mahoney wrote:

Hello people,

First of all, this might help some...

HW: rpxlite_dw mpc850
SW: linux 2.4 monta vista

I cut my board's consumption by 800mW by
1) taking off the power leds (100mA)
2) bypassing the power regulator (700mA)

I give 2 sources of current to the board: a 5V and a 3.3V, hence
modelising an ideal regulator. Turns out that the board regulator has
a 66% efficiency.

quoted

quoted

Well the 2.4 Linux kernel does not support runtime modifications to
the clock rate. So what's the point of playing with CSCR?

If the CPU is dozing The kernel will never know we changed it as long as
we change it back when the CPU wakes up.

I 100% agree with you... But it doesn't work... Here are the results I
get:

SCCR[DFHL]:SCCR[DFNL]   | Results
(clock divisers)        |
________________________|_______________________

2x:2x                   Works fine

1x:2x                   Never wakes up

1x:64x                  Kernel oopses
output: "Caused by (from SRR1=40001000): Transfer error ack signal"

SCCR[PRQEN] was '1' for all these tests.

Conn: could you give me the complete values of SCCR and PLPRCR registers?

Thanks again,

Pat Mahoney

I hope this helps

	Conn

--

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Conn Clark
Engineering Stooge				clark@esteem.com
Electronic Systems Technology Inc.		www.esteem.com


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