Dan Malek writes:

IMHO, a tlb miss handler design should simply emulate a hardware implementation,
and fetch the PTE entries into the TLB cache as quickly and efficiently as
possible.  You are typically loading valid, ready to use PTEs in a much higher
proportion to invalid ones, and I don't like the normal fast path cluttered
by the overhead of checking the special cases that require more work.

Well, simpler is better with a TLB miss handler, for sure.

However, in the context of 4xx, if we load an entry into the TLB with
the valid bit clear, all that will happen is that the cpu will give us
the same TLB miss exception again immediately.  So that doesn't get us
anywhere at all.

Paul.

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