Brad Boyer wrote:

quoted

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question 4. assuming I was willing to deliver a clean, complete LE
enabling patch (including devices that are relevant to me), as a compile
time config option and maintain that patch, what would be the primary
obstacle to inclusion in the main line.

The objection to being an arch that attempts to support both LE and BE.

Note that we already have a precedent: mips and mipsel, both in arch/mips/.

And SH too, iirc.  I know it can be done.  But do we want to do it is the
question.

At least in the case of SH, there's a good reason. There's an external pin
that controls the native endianness of the processor, and most setups just
have it forcibly pulled high or low. I suspect the MIPS is the same reason,
since it's used in similar situations. We don't have that excuse with ppc.
Someone would have to come up with an excuse along the lines of "existing
hardware won't work unless we do this" like it would have been for SH.
(I had to work with the SH4e as used by Sega in the Dreamcast...)

well, this is in the context of a multi-CPU type (x86/ppc, sparc/ppc,
ppc/ppc, mips/ppc) shared memory multicomputer.

when dealing w/ direct mapped, shared memory, uniformity of endian-ness
makes many multicomputer problems easier to solve.(not to mention easier
for the customer to program...)




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