Re: I-cache flushing on the 7400

On Sat, Mar 31, 2001 at 07:51:55PM +0200, Gabriel Paubert wrote:

quoted

	LI_PHYS( r2,split_store_patch )
	stw     r4,0(r2)			// store instruction
	dcbst   0,r2				// Flush cache
	sync
	icbi    0,r2
	isync

	.... some instructions and then a rfi to split_store_patch ....
	rfi

split_store_patch:
	nop

It should, while actually the isync does not seem necessary since rfi
is a context synchronizing instruction (rfi and sc include implicitly the
equivalent of an isync).

Yes, but in this case the rfi instruction is within the same cache-line
as the nop. I think I need the extra isync to make sure the cache
line in question is not touched before the invalidation is completed.

/Samuel


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