quoted

It would be cleaner to have the page mapped with a non-cacheable
mapping while the idle task is clearing it but you still have to be
careful about cache inconsistencies, particularly if the page is
mapped twice and one mapping is cacheable and the other isn't.

It might be interesting to try using a DMA engine on MPC 106/107 systems
to clear pages in the background. I've seen some simulations which
suggest that this could be a big win, but I'd have to spend a while
digging through the IEEE archives to find them again.

I didn't find any mention of a DMA engine in the MPC106... Or did I miss
something ?

Ben.


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