Re: PATCH: improved processor config for G3s

On   4 Sep, this message from Gabriel Paubert echoed through cyberspace:

quoted

Later on, a Moto person told me there was no known grackle bug about
store gathering, but that the CPU ABE was needed for proper operations. I
also suspect that store gathering increase the effect of PCI write
posting, and older versions of the Adaptec drivers were not correctly
taking this into account on sime timing critical accesses.

I'd rather take the Moto version. The problem is that store gathering
should be inhibited if there is an eieio instruction between two
successive stores which may be gathered. However, the eieio instruction
is not propagated to the bus by all processors, it is by the 604 and 7400
(and 601 IIRC), not by the 603/603e/750. I can't remember offhand if ABE
enables eieio broadcasts on the 750, but it seems so from what Motorola
claims.

IBM's 740/750 User's Manual states on page 2-12, in the table about ABE:

 "Affected instructions are eieio, sync, dcbi, dcbf and dcbst. A sync
 instruction completes only after a successfull broadcast. Execution of
 eieio causes a brodcast that may be used to prevent any external
 devices, such as a bus bridge chip, from store gathering"

So it seems that to prevent store gathering in bus bridges across eieio
on the 750, you need to set ABE.

Michel

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