Re: rtc again...

On RS/6000 CHRP (RS/6000 Platform Architecture), RTAS provides
freeze-time-base and thaw-time-base calls which signal all of the
processors inan SMP complex to stop and start the TB.  I do not know of
any functionality within the PowerPC architecture which would allow
processors to coordinate their TBs without some external intervention.

Normally AIX boot freezes the TB, zeroes the TB on each processor,
and then starts the timebase synchronized.  Because the functionality is
part of RTAS, this can be done at any time.  I do not know what PreP SMP
systems do and I know that Apple discourages use of RTAS because it is not
intended to work.

On recent Core99 machines, Apple has a HW timer in the KeyLargo ASIC that
can be used to sync timebases. (It looks like a 64 bits bus-cycle timer,
but I'm not completely sure yet). There's also, I beleive, the OpenPIC timer.

Ben.


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