Dan Malek wrote:

Ralph Blach wrote:

quoted

This will NOT work because for Level interrupts, the ISR will cannot be
reset until
the interrupting source is cleared.

It works for Level interrupts on the 8xx and 8260.......

quoted

The ack to reset the ISR for interrupt must go in the

ppcxxx_aic_enable

So, put it there.  All of these functions should be unique to
the 405GP interrupt controller.  You are free to implement this
as you wish.

        -- Dan

I'll take care of the problem in the 405gp version of these functions, but there
are also 403 specific versions of the functions.  I've seen various people on this
mailing list posting about 4xx processors (other than 405), but I haven't figured
out if there is anyone who is at the center of 401 and/or 403 development and
haven't found the info in the various FAQs yet.  Is there any such person?

Thanks,

-Frank
--
Frank Rowand [off-list ref]
MontaVista Software, Inc

** Sent via the linuxppc-embedded mail list. See http://lists.linuxppc.org/