[PATCH 3/4] wifi: ath9k: batch the read-modify-writes of a channel change
From: Nerijus Bendžiūnas <hidden>
Date: 2026-08-29 05:44:21
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Subsystem:
atheros ath generic utilities, qualcomm atheros ath9k wireless driver, the rest · Maintainers:
Jeff Johnson, Toke Høiland-Jørgensen, Linus Torvalds
ar5008_hw_set_delta_slope() and ath9k_hw_start_nfcal() both issue a run of read-modify-writes with nothing between them that reads a register back. Both run on every channel change, and on the USB devices each REG_RMW is its own WMI command. Wrap the two runs in the RMW buffer so the transport sends each as a single command. PCI does not install the buffer callbacks, so ENABLE_REG_RMW_BUFFER() and REG_RMW_BUFFER_FLUSH() are empty there and the writes are issued exactly as before. Signed-off-by: Nerijus Bendžiūnas <redacted> --- drivers/net/wireless/ath/ath9k/ar5008_phy.c | 2 ++ drivers/net/wireless/ath/ath9k/calib.c | 2 ++ 2 files changed, 4 insertions(+)
diff --git a/drivers/net/wireless/ath/ath9k/ar5008_phy.c b/drivers/net/wireless/ath/ath9k/ar5008_phy.c
index 7a45f5f62826..af05dcf95a61 100644
--- a/drivers/net/wireless/ath/ath9k/ar5008_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar5008_phy.c@@ -868,6 +868,7 @@ static void ar5008_hw_set_delta_slope(struct ath_hw *ah, ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man, &ds_coef_exp); + ENABLE_REG_RMW_BUFFER(ah); REG_RMW_FIELD(ah, AR_PHY_TIMING3, AR_PHY_TIMING3_DSC_MAN, ds_coef_man); REG_RMW_FIELD(ah, AR_PHY_TIMING3,
@@ -882,6 +883,7 @@ static void ar5008_hw_set_delta_slope(struct ath_hw *ah, AR_PHY_HALFGI_DSC_MAN, ds_coef_man); REG_RMW_FIELD(ah, AR_PHY_HALFGI, AR_PHY_HALFGI_DSC_EXP, ds_coef_exp); + REG_RMW_BUFFER_FLUSH(ah); } static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c
index b4ab85bd7895..73c63ab32d53 100644
--- a/drivers/net/wireless/ath/ath9k/calib.c
+++ b/drivers/net/wireless/ath/ath9k/calib.c@@ -224,6 +224,7 @@ void ath9k_hw_start_nfcal(struct ath_hw *ah, bool update) if (ah->caldata) set_bit(NFCAL_PENDING, &ah->caldata->cal_flags); + ENABLE_REG_RMW_BUFFER(ah); REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_ENABLE_NF);
@@ -235,6 +236,7 @@ void ath9k_hw_start_nfcal(struct ath_hw *ah, bool update) AR_PHY_AGC_CONTROL_NO_UPDATE_NF); REG_SET_BIT(ah, AR_PHY_AGC_CONTROL(ah), AR_PHY_AGC_CONTROL_NF); + REG_RMW_BUFFER_FLUSH(ah); } int ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
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2.55.0