-----Original Message-----
From: Arnd Bergmann <arnd@arndb.de>
Sent: Tuesday, October 5, 2021 5:59 PM
To: Pkshih <pkshih@realtek.com>
Cc: Arnd Bergmann <arnd@arndb.de>; Kalle Valo <redacted>;
linux-wireless@vger.kernel.org
Subject: Re: [PATCH v6 03/24] rtw89: add core and trx files

On Tue, Oct 5, 2021 at 11:32 AM Pkshih [off-list ref] wrote:

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Cc: Pkshih <pkshih@realtek.com>; Arnd Bergmann <arnd@arndb.de>;

linux-wireless@vger.kernel.org

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Arnd, what do you suggest? Is __always_inline good solution for this? I
think we should at least add a comment explaining why it's needed.

__always_inline can make sense to force the compiler to behave
sanely if it doesn't work it out by itself, and I think that is how this
function was meant to be used: the __compiletime_error in bitfield.h
is intended to find any callers that have a non-constant argument,
because that would result in horrible code.

I would suggest looking at the object code that you get with -Os after
the added __always_inline, just to make sure that this isn't also
horrible.

I check the function rtw89_core_fill_txdesc() which uses these macros.
With inline, the object code size is 0x1AF. With __always_inline and
-Os, the size is 0x1A4. (x86-64 platform)

Compare the object codes side-by-side, they are almost the same except
to some instructions. I think this is because the inline function
I apply __always_inline contains only a simple statement.

Ok. Did you check the output for the configuration that showed the
problem as well, after adding __always_inline? There are certain
compile-time options that could cause the code to become unoptimized,
e.g. KASAN, in addition to the OPTIMIZE_FOR_SIZE.

Summarize object code size of the combinations:

ccflag              default           -Os
======              =======           =============
inline              0x1AF             X
always_inline      0x1AA             0x1A4

With default ccflag, the difference of inline and always_inline is a
je/jne instruction for 'if (!desc_info->en_wd_info)'. The always_inline
doesn't affect the part that use RTW89_SET_TXWD().

Compare always_inline row, the case of default ccflag uses movzbl (4 bytes),
but -Os case uses mov (3 bytes).

By the results, -Os affect the object code size. always_inline doesn't
affect the code, but affect the instruction (je/jne) nearby.


I use Ubuntun kernel that doesn't enable KASAN.
# CONFIG_KASAN is not set

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+#define RTW89_SET_TXWD_BODY_WP_OFFSET(txdesc, val) \
+ RTW89_SET_TXWD(txdesc, val, 0x00, GENMASK(31, 24))
+#define RTW89_SET_TXWD_BODY_MORE_DATA(txdesc, val) \
+ RTW89_SET_TXWD(txdesc, val, 0x00, BIT(23))
+#define RTW89_SET_TXWD_BODY_WD_INFO_EN(txdesc, val) \
+ RTW89_SET_TXWD(txdesc, val, 0x00, BIT(22))
+#define RTW89_SET_TXWD_BODY_FW_DL(txdesc, val) \
+ RTW89_SET_TXWD(txdesc, val, 0x00, BIT(20))

I would personally write this without the wrappers, instead defining the
bitmask macros as the masks and then open-coding the
le32p_replace_bits() calls instead, which I would find more
intuitive while it avoids the problem with the bitmasks.

Use these macros can address offset and bit fields quickly.
How about I use macro instead of inline function? Like,

#define RTW89_SET_TXWD (txdesc, val, offset, mask) \
do { \
        u32 *txd32 = (u32 *)txdesc; \
        le32p_replace_bits((__le32 *)(txd32 + offset), val, mask); \
} while (0)

That would obviously address the immediate bug, but I think
using le32p_replace_bits() directly here would actually be
more readable, after you define the descriptor layout using
a structure with named __le32 members to replace the offset.

I will remove the wrapper and use le32p_replace_bits() directly.

I don't plan to use structure, because these data contain bit-fields.
Then, I need to maintain little-/big-endian formats, like

struct foo {
#if BIG_ENDINA
	__le32 msb:1;
	__le32 rsvd:30;
	__le32 lsb:1;
#else
	__le32 lsb:1;
	__le32 rsvd:30;
	__le32 msb:1;
#endif
};

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Going back one more step, I see that that rtw89_core_fill_txdesc()
manipulates the descriptor fields in-memory, which also seems
like a bad idea: The descriptor is mapped as cache-coherent,
so on machines with no coherent DMA (i.e. most ARM or MIPS
machines), that is uncached memory, and writing the descriptor
using a series of read-modify-write cycles on uncached memory
will be awfully slow. Maybe the answer is to just completely
replace the descriptor access.

I'll think if we can use chached memory with single_map/unmap for
descriptor. That would improve the performance.

Using dma_unmap_single() with its cache flush may not work
correctly if the descriptor fields have to be written in a particular
order. Usually the last field in a descriptor contains a 'valid'
bit that must not be observed by the hardware before the rest
is visible. The cache flush however would not guarantee the
order of the update.

Is it possible to flush cache twice? Writing the fields other
than 'valid' bit, and do wmb() and first flush. Then, set 'valid' bit,
and do second flush.

It would also likely be slower than dma_alloc_coherent() on
machines that have cache-coherent PCI, such as most x86.

The best way is usually to construct the descriptor one word
at a time in registers, and write that word using WRITE_ONCE(),
with an explict dma_wmb() before the final write that makes
the descriptor valid.

Thanks for the guideline. 

Fortunately, descriptor of this hardware uses circular ring buffer with
read/write index instead of 'valid' bit. To issue a packet with descriptor
to hardware, we fill descriptor and fill address of skb as well, and then
update write index (a register) to trigger hardware to start DMA this
packet. So, I think it is possible to use dma_map_single().

Anyway, I will try both methods later.

Thank you
--
Ping-Ke