On 02/02/2015 11:47 AM, Johannes Berg wrote:

On Mon, 2015-02-02 at 11:36 -0800, Peter Oh wrote:

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On 02/02/2015 11:22 AM, Johannes Berg wrote:

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You basically have the following sequence:

iowrite()
ioread()

If you look, you'll see that iowrite() is actually done (or should

be,

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or perhaps with appropriate syncs) on an uncached mapping.

since it's mmio, iowrite will be map to write, not out which is

cached

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mapping.
That's why we address "posted write" here.
If it's un-cached mapping which is volatile, we don't even need

ioread.

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No, this isn't true - "posted write" in the context of this discussion
is about the PCIe bus. Memory writes that go through cache aren't
referred to as "posted writes", those are just (cached) memory writes.

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    As a result,
the only thing you care about here is the PCIe bus, not the CPU

cache

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flush. And from there on that's just a question of PCIe bus

semantics.

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So how does ioread guarantee PCIe bus transaction done?

That's how PCIe works, operations are serialized, and read() has to

wait

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for a response from the device

do you know which mechanism or which instruction set makes read() wait
for a response from the device?

I have no idea. I assume it's just like a DRAM read, the CPU stalls
while there's no response.

My explanation in this thread is all about how read() guarantees the 
wait for a response from the device, therefore why mb() - replace from 
wmb at patch set 2 - is compatible to read().
Briefly speaking,
read() -> dsb 'st' -> cpu (actually axi master in cpu) holding axi bus 
-> cpu post write buffer on axi bus -> axi bus (axi slave which is PCIe 
device) signals write completion when write transactions completed in 
write response channel ->  cpu release axi bus -> cpu program counter 
(pc) proceeds the next to read.

the exact same routines happen with mb().
mb() -> dsb 'st' -> cpu (actually axi master in cpu) holding axi bus -> 
cpu post write buffer on axi bus -> axi bus (axi slave which is PCIe 
device) signals write completion when write transactions completed in 
write response channel ->  cpu release axi bus -> cpu program counter 
(pc) proceeds the next to read.

Since axi bus master is waiting (blocking) for write completion signal 
from axi slave (PCIe device), this is how read() and mb() guarantee 
write command reaches to the device.

johannes


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Regards,
Peter