Andreas Schwab [off-list ref] writes:

Larry Finger [off-list ref] writes:

quoted

On 05/31/2011 10:54 AM, Andreas Schwab wrote:

quoted

Larry Finger[off-list ref]  writes:

quoted

 From the traceback, it must be the serdes_pll_device read that failed.

Why not ssb_pcicore_polarity_workaround (note r4 == 0x134)?

Mainly because the last two steps in the traceback are

[c2ca5c40] [f2146244] ssb_pcie_read+0x4c/0x54 [ssb]
[c2ca5c50] [f2146440] ssb_pcicore_serdes_workaround+0x1c/0x170 [ssb]

Which exactly is what ssb_pcicore_polarity_workaround is doing.

0000022c <ssb_pcicore_serdes_workaround>:
 22c:   94 21 ff e0     stwu    r1,-32(r1)
 230:   7c 08 02 a6     mflr    r0
 234:   38 80 02 04     li      r4,516
 238:   90 01 00 24     stw     r0,36(r1)
 23c:   bf a1 00 14     stmw    r29,20(r1)
 240:   7c 7f 1b 78     mr      r31,r3
 244:   4b ff fd bd     bl      0 <ssb_pcie_read>

Andreas.

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Andreas Schwab, schwab@linux-m68k.org
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