[PATCH v4 2/4] arm64: dts: intel: agilex5: add USB3.1 controller node
From: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
Date: 2026-09-04 08:53:41
Also in:
linux-devicetree, lkml
Subsystem:
arm/socfpga architecture, the rest · Maintainers:
Dinh Nguyen, Linus Torvalds
Add a DTS node for the Synopsys DWC3 USB3.1 controller on the Agilex5 SoC. Place it under a simple-bus with a 40-bit dma-ranges window (#address-cells = 2) to match the USB DMA address width of the interconnect. Enable it in host mode on the SoCDK board. ref and suspend both use AGILEX5_USB31_SUSPEND_CLK because they share the same hardware clock source on this SoC. Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com> --- .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 35 +++++++++++++++++++ .../boot/dts/intel/socfpga_agilex5_socdk.dts | 5 +++ 2 files changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index f54767d1526e..523f722a2a64 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi@@ -493,6 +493,41 @@ usb0: usb@10b00000 { status = "disabled"; }; + usb31_bus: usb-bus@11000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x0 0x11000000 0x0 0x100000>; + /* + * USB interconnect DMA is limited to 40-bit addresses + * (1 TiB window from 0). + */ + dma-ranges = <0x0 0x0 0x0 0x100 0x0>; + + usb31: usb@0 { + compatible = "altr,agilex5-dwc3"; + reg = <0x0 0x0 0x0 0x100000>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + /* + * ref and suspend share the same hardware + * source; reuse the published suspend clock ID. + */ + clocks = <&clkmgr AGILEX5_USB31_BUS_CLK_EARLY>, + <&clkmgr AGILEX5_USB31_SUSPEND_CLK>, + <&clkmgr AGILEX5_USB31_SUSPEND_CLK>; + clock-names = "bus_early", "ref", "suspend"; + resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; + reset-names = "core", "ecc"; + iommus = <&smmu 7>; + phys = <&usbphy0>, <&usbphy0>; + phy-names = "usb2-phy", "usb3-phy"; + maximum-speed = "super-speed"; + snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; + status = "disabled"; + }; + }; + watchdog0: watchdog@10d00200 { compatible = "snps,dw-wdt"; reg = <0x10d00200 0x100>;
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index 1e9b87d96765..aa9294494421 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts@@ -109,6 +109,11 @@ &usb0 { disable-over-current; }; +&usb31 { + dr_mode = "host"; + status = "okay"; +}; + &watchdog0 { status = "okay"; };
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2.49.GIT