Thread (105 messages) 105 messages, 10 authors, 2020-12-22

Re: [PATCH v1 00/30] Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs

From: Ulf Hansson <hidden>
Date: 2020-11-13 14:46:24
Also in: dri-devel, linux-devicetree, linux-media, linux-mmc, linux-pwm, linux-samsung-soc, linux-tegra, lkml

On Thu, 12 Nov 2020 at 23:14, Dmitry Osipenko [off-list ref] wrote:
12.11.2020 23:43, Thierry Reding пишет:
quoted
quoted
The difference in comparison to using voltage regulator directly is
minimal, basically the core-supply phandle is replaced is replaced with
a power-domain phandle in a device tree.
These new power-domain handles would have to be added to devices that
potentially already have a power-domain handle, right? Isn't that going
to cause issues? I vaguely recall that we already have multiple power
domains for the XUSB controller and we have to jump through extra hoops
to make that work.
I modeled the core PD as a parent of the PMC sub-domains, which
presumably is a correct way to represent the domains topology.

https://gist.github.com/digetx/dfd92c7f7e0aa6cef20403c4298088d7
That could make sense, it seems.

Anyway, this made me realize that
dev_pm_genpd_set_performance_state(dev) returns -EINVAL, in case the
device's genpd doesn't have the ->set_performance_state() assigned.
This may not be correct. Instead we should likely consider an empty
callback as okay and continue to walk the topology upwards to the
parent domain, etc.

Just wanted to point this out. I intend to post a patch as soon as I
can for this.

[...]

Kind regards
Uffe
Keyboard shortcuts
hback out one level
jnext message in thread
kprevious message in thread
ldrill in
Escclose help / fold thread tree
?toggle this help