[PATCH v14 05/14] x86/hw_breakpoints: Add arch_modify_local_hw_breakpoint_addr() API
From: "Masami Hiramatsu (Google)" <mhiramat@kernel.org>
Date: 2026-08-30 14:27:51
Also in:
linux-doc, linux-perf-users, lkml
Subsystem:
the rest, x86 architecture (32-bit and 64-bit) · Maintainers:
Linus Torvalds, Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen
From: Jinchao Wang <redacted> Wprobe needs to move an active per-CPU watchpoint without releasing and reserving its hardware slot. Add arch_modify_local_hw_breakpoint_addr() as the architecture backend for modify_local_hw_breakpoint_addr(). It validates the new address, finds the installed local slot, and updates the hardware debug register and per-CPU shadow register. The core layer (modify_local_hw_breakpoint_addr()) handles updating bp->attr.bp_addr and counter_arch_bp(bp)->address. The caller must provide an installed local event and a valid address. Slot ownership, breakpoint type, length, mask and DR7 remain unchanged. Link: https://lore.kernel.org/all/59637b96946653393a7ad3c7de094094796b39c2.1785067572.git.wangjinchao600@gmail.com/ (local) Signed-off-by: Jinchao Wang <redacted> Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org> --- Changes in v13: - Add compiler barrier (barrier()) before checking cpu_dr7_seq to prevent hoisting the sequence check before set_debugreg(). - Clarify in commit log and code comment that the core layer manages updating bp->attr.bp_addr and counter_arch_bp(bp)->address. Changes in v11: - Return int error code instead of void. - Validate the new address using hw_breakpoint_arch_parse() before updating registers. - Increment cpu_dr7_seq in a sequence loop for NMI protection. - Return -ENOENT if the breakpoint slot is not found on the local CPU. --- arch/x86/include/asm/hw_breakpoint.h | 2 ++ arch/x86/kernel/hw_breakpoint.c | 44 ++++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+)
diff --git a/arch/x86/include/asm/hw_breakpoint.h b/arch/x86/include/asm/hw_breakpoint.h
index 0bc931cd0698..f35ec491f6dd 100644
--- a/arch/x86/include/asm/hw_breakpoint.h
+++ b/arch/x86/include/asm/hw_breakpoint.h@@ -59,6 +59,8 @@ extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused, int arch_install_hw_breakpoint(struct perf_event *bp); +int arch_modify_local_hw_breakpoint_addr(struct perf_event *bp, + unsigned long addr); void arch_uninstall_hw_breakpoint(struct perf_event *bp); void hw_breakpoint_pmu_read(struct perf_event *bp); void hw_breakpoint_pmu_unthrottle(struct perf_event *bp);
diff --git a/arch/x86/kernel/hw_breakpoint.c b/arch/x86/kernel/hw_breakpoint.c
index 3204e75dc454..2227918b0163 100644
--- a/arch/x86/kernel/hw_breakpoint.c
+++ b/arch/x86/kernel/hw_breakpoint.c@@ -129,6 +129,50 @@ int arch_install_hw_breakpoint(struct perf_event *bp) return 0; } +/* + * Modify the address of an installed perf counter breakpoint on local CPU. + * + * This updates the debug address register and per-CPU shadow state without + * changing slot allocation or DR7. The core layer (modify_local_hw_breakpoint_addr()) + * manages updating bp->attr.bp_addr and counter_arch_bp(bp)->address. + * + * Atomic: called with IRQs disabled and handles variables and registers + * local to this CPU. + */ +int arch_modify_local_hw_breakpoint_addr(struct perf_event *bp, + unsigned long addr) +{ + struct arch_hw_breakpoint hw; + struct perf_event_attr attr = bp->attr; + unsigned int seq; + int i, ret; + + lockdep_assert_irqs_disabled(); + + attr.bp_addr = addr; + ret = hw_breakpoint_arch_parse(bp, &attr, &hw); + if (ret) + return ret; + + for (i = 0; i < HBP_NUM; i++) { + if (this_cpu_read(bp_per_reg[i]) == bp) + break; + } + + if (WARN_ONCE(i == HBP_NUM, "Can't find any breakpoint slot")) + return -ENOENT; + + do { + seq = this_cpu_inc_return(cpu_dr7_seq); + this_cpu_write(cpu_debugreg[i], addr); + barrier(); + set_debugreg(addr, i); + barrier(); + } while (seq != this_cpu_read(cpu_dr7_seq)); + + return 0; +} + /* * Uninstall the breakpoint contained in the given counter. *