Thread (60 messages) 60 messages, 6 authors, 2025-11-06

Re: [RFC PATCH v6 27/29] x86/mm/pti: Implement a TLB flush immediately after a switch to kernel CR3

From: Valentin Schneider <vschneid@redhat.com>
Date: 2025-10-29 10:16:29
Also in: linux-arch, linux-arm-kernel, linux-mm, linux-riscv, lkml, loongarch, rcu

On 28/10/25 16:59, Frederic Weisbecker wrote:
Le Fri, Oct 10, 2025 at 05:38:37PM +0200, Valentin Schneider a écrit :
quoted
@@ -171,8 +172,27 @@ For 32-bit we have the following conventions - kernel is built with
     andq    $(~PTI_USER_PGTABLE_AND_PCID_MASK), \reg
 .endm

-.macro COALESCE_TLBI
+.macro COALESCE_TLBI scratch_reg:req
 #ifdef CONFIG_COALESCE_TLBI
+	/* No point in doing this for housekeeping CPUs */
+	movslq  PER_CPU_VAR(cpu_number), \scratch_reg
+	bt	\scratch_reg, tick_nohz_full_mask(%rip)
+	jnc	.Lend_tlbi_\@
I assume it's not possible to have a static call/branch to
take care of all this ?
I think technically yes, but that would have to be a per-cpu patchable
location, which would mean something like each CPU having its own copy of
that text page... Unless there's some existing way to statically optimize

  if (cpumask_test_cpu(smp_processor_id(), mask))

where @mask is a boot-time constant (i.e. the nohz_full mask).
Thanks.

--
Frederic Weisbecker
SUSE Labs
  
Keyboard shortcuts
hback out one level
jnext message in thread
kprevious message in thread
ldrill in
Escclose help / fold thread tree
?toggle this help