[PATCH v5 8/9] perf/x86: Enable NMI-source reporting for perfmon
From: Sohil Mehta <hidden>
Date: 2025-05-07 01:21:29
Also in:
kvm, linux-edac, linux-perf-users, linux-pm, lkml
Subsystem:
performance events subsystem, the rest, x86 architecture (32-bit and 64-bit) · Maintainers:
Peter Zijlstra, Ingo Molnar, Arnaldo Carvalho de Melo, Namhyung Kim, Linus Torvalds, Thomas Gleixner, Borislav Petkov, Dave Hansen
From: Jacob Pan <redacted> Program the designated PMI NMI-source vector into the local vector table for the PMU. An NMI for the PMU would directly invoke the PMI handler without polling other NMI handlers, resulting in reduced PMI delivery latency. Co-developed-by: Zeng Guang <redacted> Signed-off-by: Zeng Guang <redacted> Signed-off-by: Jacob Pan <redacted> Signed-off-by: Sohil Mehta <redacted> Reviewed-by: Kan Liang <redacted> --- v5: No significant change. --- arch/x86/events/core.c | 4 ++-- arch/x86/events/intel/core.c | 6 +++--- arch/x86/include/asm/apic.h | 1 + 3 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 031e908f0d61..42b270526631 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c@@ -1695,7 +1695,7 @@ int x86_pmu_handle_irq(struct pt_regs *regs) * This generic handler doesn't seem to have any issues where the * unmasking occurs so it was left at the top. */ - apic_write(APIC_LVTPC, APIC_DM_NMI); + apic_write(APIC_LVTPC, PERF_NMI); for_each_set_bit(idx, x86_pmu.cntr_mask, X86_PMC_IDX_MAX) { if (!test_bit(idx, cpuc->active_mask))
@@ -1737,7 +1737,7 @@ void perf_events_lapic_init(void) /* * Always use NMI for PMU */ - apic_write(APIC_LVTPC, APIC_DM_NMI); + apic_write(APIC_LVTPC, PERF_NMI); } static int
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 09d2d66c9f21..87c624686c58 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c@@ -3202,7 +3202,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) * NMI handler. */ if (!late_ack && !mid_ack) - apic_write(APIC_LVTPC, APIC_DM_NMI); + apic_write(APIC_LVTPC, PERF_NMI); intel_bts_disable_local(); cpuc->enabled = 0; __intel_pmu_disable_all(true);
@@ -3239,7 +3239,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) done: if (mid_ack) - apic_write(APIC_LVTPC, APIC_DM_NMI); + apic_write(APIC_LVTPC, PERF_NMI); /* Only restore PMU state when it's active. See x86_pmu_disable(). */ cpuc->enabled = pmu_enabled; if (pmu_enabled)
@@ -3252,7 +3252,7 @@ static int intel_pmu_handle_irq(struct pt_regs *regs) * Haswell CPUs. */ if (late_ack) - apic_write(APIC_LVTPC, APIC_DM_NMI); + apic_write(APIC_LVTPC, PERF_NMI); return handled; }
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 9bade39b5feb..b2f864e77d84 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h@@ -29,6 +29,7 @@ #define BT_NMI (APIC_DM_NMI | NMIS_VECTOR_BT) #define KGDB_NMI (APIC_DM_NMI | NMIS_VECTOR_KGDB) #define MCE_NMI (APIC_DM_NMI | NMIS_VECTOR_MCE) +#define PERF_NMI (APIC_DM_NMI | NMIS_VECTOR_PMI) /* * Debugging macros
--
2.43.0