On Mon, 7 Jun 2021, Segher Boessenkool wrote:
quoted
So the barrier which is a compiler barrier but not a machine barrier is
__atomic_signal_fence(model), but internally GCC will not treat it smarter
than an asm-with-memory-clobber today.
It will do nothing for relaxed ordering, and do blockage for everything
else. Can it do anything weaker than that?
It's a "blockage instruction" after transitioning to RTL, but before that,
on GIMPLE, the compiler sees it properly as a corresponding built-in, and
may optimize according to given memory model. And on RTL, well, if anyone
cares they'll need to invent RTL representation for it, I guess.
Alexander