On Sun, Aug 8, 2021 at 9:01 AM Vidya Sagar [off-list ref] wrote:

On 8/21/2020 9:24 AM, Rob Herring wrote:

quoted

The Designware controller has common registers to set number of fast
training sequence ordered sets. The Artpec6, Intel, and Tegra driver
initialize these register fields. Let's move the initialization to the
common setup code and drivers just have to provide the value.

There's a slight change in that the common clock mode N_FTS field is
now initialized. Previously only the Intel driver set this. It's not
clear from the code if common clock mode is used in the Artpec6 or Tegra
driver. It depends on the DWC configuration. Given the field is not
initialized while the others are, it seems unlikely common clock mode
is used.

Cc: Jesper Nilsson <jesper.nilsson@axis.com>
Cc: Lorenzo Pieralisi <redacted>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <redacted>
Cc: Thierry Reding <redacted>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
  drivers/pci/controller/dwc/pcie-artpec6.c    | 37 +++-----------------
  drivers/pci/controller/dwc/pcie-designware.c | 28 +++++++++------
  drivers/pci/controller/dwc/pcie-designware.h |  3 +-
  drivers/pci/controller/dwc/pcie-intel-gw.c   | 27 +++++---------
  drivers/pci/controller/dwc/pcie-tegra194.c   | 25 ++-----------
  5 files changed, 35 insertions(+), 85 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
index 86f4d66d8587..929448e9e0bc 100644
--- a/drivers/pci/controller/dwc/pcie-artpec6.c
+++ b/drivers/pci/controller/dwc/pcie-artpec6.c

@@ -44,13 +44,6 @@ struct artpec_pcie_of_data {

  static const struct of_device_id artpec6_pcie_of_match[];

-/* PCIe Port Logic registers (memory-mapped) */
-#define PL_OFFSET                    0x700
-
-#define ACK_F_ASPM_CTRL_OFF          (PL_OFFSET + 0xc)
-#define ACK_N_FTS_MASK                       GENMASK(15, 8)
-#define ACK_N_FTS(x)                 (((x) << 8) & ACK_N_FTS_MASK)
-
  /* ARTPEC-6 specific registers */
  #define PCIECFG                             0x18
  #define  PCIECFG_DBG_OEN            BIT(24)

@@ -289,30 +282,6 @@ static void artpec6_pcie_init_phy(struct artpec6_pcie *artpec6_pcie)
      }
  }

-static void artpec6_pcie_set_nfts(struct artpec6_pcie *artpec6_pcie)
-{
-     struct dw_pcie *pci = artpec6_pcie->pci;
-     u32 val;
-
-     if (artpec6_pcie->variant != ARTPEC7)
-             return;
-
-     /*
-      * Increase the N_FTS (Number of Fast Training Sequences)
-      * to be transmitted when transitioning from L0s to L0.
-      */
-     val = dw_pcie_readl_dbi(pci, ACK_F_ASPM_CTRL_OFF);
-     val &= ~ACK_N_FTS_MASK;
-     val |= ACK_N_FTS(180);
-     dw_pcie_writel_dbi(pci, ACK_F_ASPM_CTRL_OFF, val);
-
-     /*
-      * Set the Number of Fast Training Sequences that the core
-      * advertises as its N_FTS during Gen2 or Gen3 link training.
-      */
-     dw_pcie_link_set_n_fts(pci, 180);
-}
-
  static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie)
  {
      u32 val;

@@ -351,11 +320,14 @@ static int artpec6_pcie_host_init(struct pcie_port *pp)
      struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
      struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);

+     if (artpec6_pcie->variant == ARTPEC7) {
+             pci->n_fts[0] = 180;
+             pci->n_fts[1] = 180;
+     }
      artpec6_pcie_assert_core_reset(artpec6_pcie);
      artpec6_pcie_init_phy(artpec6_pcie);
      artpec6_pcie_deassert_core_reset(artpec6_pcie);
      artpec6_pcie_wait_for_phy(artpec6_pcie);
-     artpec6_pcie_set_nfts(artpec6_pcie);
      dw_pcie_setup_rc(pp);
      artpec6_pcie_establish_link(pci);
      dw_pcie_wait_for_link(pci);

@@ -403,7 +375,6 @@ static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)
      artpec6_pcie_init_phy(artpec6_pcie);
      artpec6_pcie_deassert_core_reset(artpec6_pcie);
      artpec6_pcie_wait_for_phy(artpec6_pcie);
-     artpec6_pcie_set_nfts(artpec6_pcie);

      for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
              dw_pcie_ep_reset_bar(pci, bar);

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 61e1faba15bf..3cb21247619c 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c

@@ -510,17 +510,6 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
  }
  EXPORT_SYMBOL_GPL(dw_pcie_link_set_max_speed);

-void dw_pcie_link_set_n_fts(struct dw_pcie *pci, u32 n_fts)
-{
-     u32 val;
-
-     val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
-     val &= ~PORT_LOGIC_N_FTS_MASK;
-     val |= n_fts & PORT_LOGIC_N_FTS_MASK;
-     dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
-}
-EXPORT_SYMBOL_GPL(dw_pcie_link_set_n_fts);
-
  static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
  {
      u32 val;

@@ -551,6 +540,23 @@ void dw_pcie_setup(struct dw_pcie *pci)
      if (pci->link_gen > 0)
              dw_pcie_link_set_max_speed(pci, pci->link_gen);

+     /* Configure Gen1 N_FTS */
+     if (pci->n_fts[0]) {
+             val = dw_pcie_readl_dbi(pci, PCIE_PORT_AFR);
+             val &= ~(PORT_AFR_N_FTS_MASK | PORT_AFR_CC_N_FTS_MASK);
+             val |= PORT_AFR_N_FTS(pci->n_fts[0]);
+             val |= PORT_AFR_CC_N_FTS(pci->n_fts[0]);
+             dw_pcie_writel_dbi(pci, PCIE_PORT_AFR, val);
+     }
+
+     /* Configure Gen2+ N_FTS */
+     if (pci->n_fts[1]) {
+             val = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
+             val &= ~PORT_LOGIC_N_FTS_MASK;
+             val |= pci->n_fts[pci->link_gen - 1];

Apologies for getting late to this change given that the change has
already been merged.
I'm wondering why is it that link_gen has to be used in deriving the
index instead of directly using '1' as the index?
Infact the for link speed greater than 2, accesses go beyond n_fts[]
array boundaries.
Since the if() check is done based on a non-zero value of pci->n_fts[1],
shouldn't the same be used for programming also?

Yes, I think you are right.

Rob