[PATCH v2 2/2] clk: tegra20: Correct PLL_C_OUT1 setup
From: Dmitry Osipenko <hidden>
Date: 2017-12-19 04:00:04
Also in:
linux-clk, lkml
Subsystem:
common clk framework, tegra clock driver, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Prashant Gaikwad, Linus Torvalds
PLL_C_OUT_1 can't produce 216 MHz defined in the init_table. Let's set it to 240 MHz and explicitly specify HCLK rate for consistency. Signed-off-by: Dmitry Osipenko <redacted> Acked-By: Peter De Schrijver <redacted> --- Change log: v2: No change. drivers/clk/tegra/clk-tegra20.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index d143a867968a..06c743988ae2 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c@@ -1019,9 +1019,9 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 0 }, { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 0 }, { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 0 }, - { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 216000000, 0 }, - { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 0 }, - { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 0 }, + { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 240000000, 0 }, + { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 240000000, 0 }, + { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 240000000, 0 }, { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 0 }, { TEGRA20_CLK_CSITE, TEGRA20_CLK_CLK_MAX, 0, 1 }, { TEGRA20_CLK_CCLK, TEGRA20_CLK_CLK_MAX, 0, 1 },
--
2.15.1