Re: [PATCH 07/12] PCI: tegra: Disable AFI dynamic clock gating
From: Manikanta Maddireddy <hidden>
Date: 2017-10-30 16:18:56
Also in:
linux-pci
Possibly related (same subject, not in this thread)
- 2017-10-30 · RE: [PATCH 07/12] PCI: tegra: Disable AFI dynamic clock gating · David Laight <hidden>
- 2017-10-30 · Re: [PATCH 07/12] PCI: tegra: Disable AFI dynamic clock gating · Manikanta Maddireddy <hidden>
- 2017-10-29 · Re: [PATCH 07/12] PCI: tegra: Disable AFI dynamic clock gating · Vidya Sagar <hidden>
- 2017-10-27 · [PATCH 07/12] PCI: tegra: Disable AFI dynamic clock gating · Manikanta Maddireddy <hidden>
On 30-Oct-17 9:28 PM, David Laight wrote:
From: Manikanta Maddireddyquoted
Sent: 27 October 2017 20:29 When there are 32 outstanding writes from AFI to memory, the outstanding write counter overflows and indicates that there are "0" outstanding write transactions. This outstanding write counter is used to generate IDLE signal to dynamically gate the AFI clock. When memory controller is under heavy load, its possible that write completions will come back to AFI after long delay and AFI write counter overflows. AFI clock gets gated even when there are outstanding transactions towards memory controller resutling in system hang. Disable dynamic clock gating of AFI clock to avoid system hang.At least some of the above really ought to be comments in the code. (and with the earlier fix for limiting the number of writes.) David
Ok, will take care of it in next version