On 26.09.2017 17:50, Jon Hunter wrote:

On 26/09/17 00:22, Dmitry Osipenko wrote:

quoted

Document DT bindings for NVIDIA Tegra AHB DMA controller that presents
on Tegra20/30 SoC's.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 .../bindings/dma/nvidia,tegra20-ahbdma.txt         | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
new file mode 100644
index 000000000000..2af9aa76ae11
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt

@@ -0,0 +1,23 @@
+* NVIDIA Tegra AHB DMA controller
+
+Required properties:
+- compatible:	Must be "nvidia,tegra20-ahbdma"
+- reg:		Should contain registers base address and length.
+- interrupts:	Should contain one entry, DMA controller interrupt.
+- clocks:	Should contain one entry, DMA controller clock.
+- resets :	Should contain one entry, DMA controller reset.
+- #dma-cells:	Should be <1>. The cell represents DMA request select value
+		for the peripheral. For more details consult the Tegra TRM's
+		documentation, in particular AHB DMA channel control register
+		REQ_SEL field.

What about the TRIG_SEL field? Do we need to handle this here as well?

I've followed APB DMA here, that HW also has TRIG_SEL but ignores it for some
reason. I think technically it should be present in the binding, yeah.

-- 
Dmitry