On Thu, Sep 08, 2016 at 11:49:31AM -0600, Stephen Warren wrote:

On 09/01/2016 01:02 PM, Stephen Warren wrote:

quoted

From: Stephen Warren <redacted>

The Synopsys DWC EQoS is a configurable IP block which supports multiple
options for bus type, clocking and reset structure, and feature list.
Extend the DT binding to define a "compatible value" for the configuration
contained in NVIDIA's Tegra186 SoC, and define some new properties and
list property entries required by that configuration.

Signed-off-by: Stephen Warren <redacted>
---
v3:
* Document legacy clock-names entries separately, and make it obvious
 they're deprecated.
* Reword the description of the "rx" clock to better describe the HW.
* Add some extra guidance for future extensions of the binding to cover
 configurations where additional RX clocks are required.
* Explicitly document the list of clocks and resets for every compatible
 value; don't miss any out.

Rob, Mark,

Does this version look good (Lars already acked it)? If so, if you could ack
it that'd be great; I want to send some U-Boot drivers that use this
binding, but don't want to do so before I know it's final.

Applied.

Rob