On 08/24, Thierry Reding wrote:

From: Vince Hsu <redacted>

Tegra114 has a HW bug that the PLLD/PLLD2 lock bit cannot be asserted when
the DIS power domain is during up-powergating process but the clamp to this
domain is not removed yet. That causes a timeout and aborts the power
sequence, although the PLLD/PLLD2 has already locked. To remove the false
alarm, we don't use the lock for PLLD/PLLD2. Just wait 1ms and treat the
clocks as locked.

Signed-off-by: Vince Hsu <redacted>
Tested-by: Jonathan Hunter <redacted>
Signed-off-by: Thierry Reding <redacted>
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Applied to clk-fixes

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