On 08/05/2013 09:38 AM, Prashant Gaikwad wrote:

On Thursday 01 August 2013 02:34 AM, Stephen Warren wrote:

quoted

On 07/31/2013 11:42 AM, Tuomas Tynkkynen wrote:

quoted

The lock bit on PLL_U does not seem to be working correctly and
sometimes never gets set when waiting for the PLL to come up.
Remove the TEGRA_PLL_USE_LOCK flag to use a constant delay.

Peter, Prashant,

I think you said that the lock bits should work on Tegra30 (albeit they
don't on Tegra20)? Can you remind me if the do/don't?

If Peter and Prashant are OK with this patch, feel free to take my ack.

Hi Tuomas,

Sorry for the delayed response. Please make sure that avdd_usb_pll 
regulator is enabled before enabling PLLU and utmip parameters are 
configured properly.

As far as I can see, avdd_usb_pll is connected to the vio_reg regulator on Cardhu,
which is marked as regulator-always-on. And the same regulator is connected to
eg. VDDIO_UART on the chip, so I presume almost nothing would work if that regulator
would not be on...

If this this regulator is not enabled then you will get this kind of 
timeout when enabling PLLU.

Thanks,
Prashant

quoted

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