Thread (9 messages) 9 messages, 4 authors, 2012-10-29

Re: [PATCH] spi: tegra: add spi driver for SLINK controller

From: Stephen Warren <hidden>
Date: 2012-10-29 15:18:02
Also in: linux-spi, lkml

On 10/26/2012 12:49 PM, Laxman Dewangan wrote:
Thanks Stephen for review.
I have taken care of almost all feedback. Some of having my below comments.

On Tuesday 23 October 2012 01:32 AM, Stephen Warren wrote:
quoted
On 10/18/2012 04:47 AM, Laxman Dewangan wrote:
quoted
Tegra20/Tegra30 supports the spi interface through its SLINK
controller. Add spi driver for SLINK controller.
quoted
quoted
+     val_write = SLINK_RDY;
+     val_write |= (val&  SLINK_FIFO_ERROR);
Why not just always set SLINK_FIFO_ERROR; does it have to be set in the
write only if the status was previously asserted? If that is true, how
do you avoid a race condition where the bit gets set in SLINK_STATUS
after you read it but before you write to clear it?
Status gets updated together. There is no steps of updating status.
Sorry, I don't understand this answer.
quoted
quoted
+     spin_lock_irqsave(&tspi->lock, flags);
+     if (err) {
+             dev_err(tspi->dev,
+                     "DmaXfer: ERROR bit set 0x%x\n",
tspi->status_reg);
+             dev_err(tspi->dev,
+                     "DmaXfer 0x%08x:0x%08x:0x%08x\n",
tspi->command_reg,
+                             tspi->command2_reg,
tspi->dma_control_reg);
+             tegra_periph_reset_assert(tspi->clk);
+             udelay(2);
+             tegra_periph_reset_deassert(tspi->clk);
Do we /have/ to reset the SPI block; can't we just disable it in the
control register, clear all status, and re-program it from scratch?

If at all possible, I would like to avoid introducing any new use of
tegra_periph_reset_{,de}assert, since that API has no standard subsystem
equivalent (or if it does, isn't hooked into the standard subsystem
yet), and hence means this driver relies on a header file currently in
arch/arm/mach-tegra/include/mach, and we need to move or delete all such
headers in order to support single zImage.
Is there a way to support the reset of controller. We will need this
functionality.
Why do we need to reset the controller at all; can't we simply program
all the (few) configuration registers? Are there HW bugs that hang the
controller and require a reset or something?

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