Hi Mark,

On Mon, Oct 25, 2021 at 2:17 AM Mark Rutland [off-list ref] wrote:

Hi,

On Sun, Oct 24, 2021 at 06:51:56PM -0700, Brad Larson wrote:

quoted

Add Pensando common and Elba SoC specific device nodes

Signed-off-by: Brad Larson <redacted>

[...]

quoted

+     timer {
+             compatible = "arm,armv8-timer";
+             interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
+                                     IRQ_TYPE_LEVEL_LOW)>,
+                          <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
+                                     IRQ_TYPE_LEVEL_LOW)>,
+                          <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
+                                     IRQ_TYPE_LEVEL_LOW)>,
+                          <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
+                                     IRQ_TYPE_LEVEL_LOW)>;
+     };

The GIC_CPU_MASK_SIMPLE() stuff is meant for GICv2, but as below you
have GICv3, where this is not valid, so this should go.

Also, beware that GIC_CPU_MASK_SIMPLE(1) means a single CPU, which
doesn't mak sense for the 16 CPUs you have.

Thanks for pointing this out.  Elba SoC is a GICv3 implementation and looking
at other device tree files we should be using this:

        timer {
                compatible = "arm,armv8-timer";
                interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(16) |
                                        IRQ_TYPE_LEVEL_LOW)>,
                             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(16) |
                                        IRQ_TYPE_LEVEL_LOW)>,
                             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(16) |
                                        IRQ_TYPE_LEVEL_LOW)>,
                             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(16) |
                                        IRQ_TYPE_LEVEL_LOW)>;
        };

quoted

+             gic: interrupt-controller@800000 {
+                     compatible = "arm,gic-v3";
+                     #interrupt-cells = <3>;
+                     #address-cells = <2>;
+                     #size-cells = <2>;
+                     ranges;
+                     interrupt-controller;
+                     reg = <0x0 0x800000 0x0 0x200000>,      /* GICD */
+                           <0x0 0xa00000 0x0 0x200000>;      /* GICR */
+                     interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+
+                     gic_its: msi-controller@820000 {
+                             compatible = "arm,gic-v3-its";
+                             msi-controller;
+                             #msi-cells = <1>;
+                             reg = <0x0 0x820000 0x0 0x10000>;
+                             socionext,synquacer-pre-its =
+                                                     <0xc00000 0x1000000>;
+                     };
+             };

Is there any shared lineage with Synquacer? The commit message didn't
describe this quirk.

There is no shared lineage with Synqacer.  We are solving the same issue
with the same mechanism.  I'll add a comment to this DTS node.

Thanks,
Brad