On Thu, Jun 21, 2012 at 07:11:42AM -0700, Brandt, Chris wrote:

quoted

At least for the sh7757 and sh7372.

Also for the sh7724 (ie, only the sh7757 can run at full bus speed by setting CLKDIV=0xF which no other part can....yet)

Thanks.

But, with this new patch applied:

quoted

 	if (!ret) {
 		host->clk = clk_get_rate(host->hclk);
-		host->mmc->f_max = host->clk / 2;
+		host->mmc->f_max = p->sup_pclk ? host->clk : host->clk / 2;
 		host->mmc->f_min = host->clk / 512;
 	}

Then there's no need to check for p->sup_pclk in sh_mmcif_clock_control() because if (clk = host->clk) then p->sup_pclk can be assumed to be set.

-	if (p->sup_pclk && clk = host->clk)
+	if (clk = host->clk)
		sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK);
	else
		sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR &
				((fls(DIV_ROUND_UP(host->clk,
						   clk) - 1) - 1) << 16));


But, that's probably more along the lines of driver cleanup I guess.

Thanks, I'll add that.