[PATCH v2 03/15] serial: 8250_mxpcie: enable enhanced mode and program FIFO trigger levels
From: Crescent Hsieh <hidden>
Date: 2026-07-01 03:43:44
Also in:
lkml
Subsystem:
8250/16?50 (and clone uarts) serial driver, the rest, tty layer and serial drivers · Maintainers:
Greg Kroah-Hartman, Linus Torvalds, Jiri Slaby
The MUEx50 UART provides an enhanced register set and programmable FIFO trigger levels for RX, TX, and flow control. Enable enhanced mode during port startup and program the MUEx50 FIFO trigger registers according to the configured port settings. Clear the programmed state again during shutdown to restore the default UART configuration. The TX FIFO write pointer and read pointer are driven by different clocks. Clear the FIFOs repeatedly during startup so both pointers are reset before programming the trigger levels. Signed-off-by: Crescent Hsieh <redacted> --- drivers/tty/serial/8250/8250_mxpcie.c | 59 +++++++++++++++++++++++++++ 1 file changed, 59 insertions(+)
diff --git a/drivers/tty/serial/8250/8250_mxpcie.c b/drivers/tty/serial/8250/8250_mxpcie.c
index c82d3149a03d..c1fc5eba0c58 100644
--- a/drivers/tty/serial/8250/8250_mxpcie.c
+++ b/drivers/tty/serial/8250/8250_mxpcie.c@@ -48,6 +48,19 @@ #define MOXA_PUART_BASE_BAUD 921600 #define MOXA_PUART_OFFSET 0x200 +/* Special Function Register (SFR) */ +#define MOXA_PUART_SFR 0x07 +#define MOXA_PUART_SFR_950 BIT(5) + +/* Enhanced Function Register (EFR) */ +#define MOXA_PUART_EFR 0x0A +#define MOXA_PUART_EFR_ENHANCED BIT(4) + +#define MOXA_PUART_TTL 0x10 /* Tx Interrupt Trigger Level */ +#define MOXA_PUART_RTL 0x11 /* Rx Interrupt Trigger Level */ +#define MOXA_PUART_FCL 0x12 /* Flow Control Low Trigger Level */ +#define MOXA_PUART_FCH 0x13 /* Flow Control High Trigger Level */ + #define MOXA_GPIO_DIRECTION 0x09 #define MOXA_GPIO_OUTPUT 0x0A
@@ -132,6 +145,49 @@ static void mxpcie8250_set_interface(struct mxpcie8250 *priv, iowrite8(cval, uir_addr); } +static int mxpcie8250_startup(struct uart_port *port) +{ + struct uart_8250_port *up = up_to_u8250p(port); + int ret; + + ret = serial8250_do_startup(port); + if (ret) + return ret; + + /* + * The TX FIFO write pointer (w_ptr) and read pointer (r_ptr) + * are driven by different clocks: w_ptr uses the PCIe clock + * and r_ptr uses the UART clock. When TX FIFO flush is requested, + * w_ptr may be cleared before r_ptr, so the UART can still observe + * pending TX data. + * + * It is recommended to clear the FIFOs at least 5 times to ensure + * both pointers are reset. + */ + for (unsigned int i = 0; i < 5; ++i) + serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); + + serial_out(up, MOXA_PUART_EFR, MOXA_PUART_EFR_ENHANCED); + serial_out(up, MOXA_PUART_SFR, MOXA_PUART_SFR_950); + + serial_out(up, MOXA_PUART_TTL, 0); + serial_out(up, MOXA_PUART_RTL, 96); + serial_out(up, MOXA_PUART_FCL, 16); + serial_out(up, MOXA_PUART_FCH, 110); + + return 0; +} + +static void mxpcie8250_shutdown(struct uart_port *port) +{ + struct uart_8250_port *up = up_to_u8250p(port); + + serial_out(up, MOXA_PUART_EFR, 0); + serial_out(up, MOXA_PUART_SFR, 0); + + serial8250_do_shutdown(port); +} + static void mxpcie8250_init_board(struct pci_dev *pdev, struct mxpcie8250 *priv) { void __iomem *bar2_base = priv->bar2_base;
@@ -226,6 +282,9 @@ static int mxpcie8250_probe(struct pci_dev *pdev, const struct pci_device_id *id up.port.iobase = 0; up.port.regshift = 0; + up.port.startup = mxpcie8250_startup; + up.port.shutdown = mxpcie8250_shutdown; + for (unsigned int i = 0; i < num_ports; i++) { mxpcie8250_setup_port(pdev, priv, &up, i);
--
2.45.2