Re: [PATCH 08/15] dt-bindings: clock: Document ma35d1 clock controller bindings
From: Jacky Huang <hidden>
Date: 2023-03-17 09:52:50
Also in:
linux-clk, linux-devicetree, lkml
Dear Krzysztof, Thanks for your advice. On 2023/3/17 下午 05:13, Krzysztof Kozlowski wrote:
On 17/03/2023 04:47, Jacky Huang wrote:quoted
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+ + nuvoton,pll-mode: + description: + A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL, + EPLL, and VPLL in sequential. The operation mode value 0 is for + integer mode, 1 is for fractional mode, and 2 is for spread + spectrum mode. + $ref: /schemas/types.yaml#/definitions/uint32-array + maxItems: 5 + items: + minimum: 0 + maximum: 2Why exactly this is suitable for DT?I will use strings instead.I have doubts why PLL mode is a property of DT. Is this a board-specific property?
CA-PLL has mode 0 only. DDRPLL, APLL, EPLL, and VPLL have the same PLL design that supports integer mode, fractional mode, and spread spctrum mode. The PLL mode is controlled by clock controller register. I think it's not board-specific.
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+ + nuvoton,sys: + description: + Phandle to the system management controller. + $ref: "/schemas/types.yaml#/definitions/phandle-array"Drop quotes. You need here constraints, look for existing examples.I would like to modify this as: nuvoton,sys: description: Use to unlock and lock some clock controller registers. The lock control register is in system controller. $ref: /schemas/types.yaml#/definitions/phandle-array items: - items: - description: phandle to the system controller.In such case you do not have array. Just make it phandle and drop the items.
Thank you. So, I will rewrite it as nuvoton,sys: description: Use to unlock and lock some clock controller registers. The lock control register is in system controller. $ref: /schemas/types.yaml#/definitions/phandle
Best regards, Krzysztof
Best regards, Jacky Huang