Re: [PATCH] serial: meson: make the current driver compatible with S4

Hi,

On Mon, Dec 6, 2021 at 11:02 AM xianwei.zhao [off-list ref] wrote:

Because S4 UART use a different clock source, the baud rate calculation need to be updated.
Reset the UART during initialization to clear previous status.

Could you please explain why it is needed (is the divide-by-three
divider broken, does this patch decrease clock jitter, ...)?
Think of it like this: if I add another Amlogic board.dts tomorrow,
then how do I know when the "xtal_tick_en" property needs to be set?

I found that the public datasheet for the A311D SoC already mentions
AML_UART_BAUD_XTAL_TICK and AML_UART_BAUD_XTAL_DIV2 but so far UART is
working fine on that SoC even without this patch.

[...]

+       val = readl_relaxed(port->membase + AML_UART_REG5);

The old logic worked like this:
- calculate the new register values
- write "val" to the register

The new logic uses many extra steps:
- read the existing register value
- mask off some bits in the "val" variable
- update some bits in the "val" variable based on the calculations below
- write "val" to the register

Is there any reason why we need to change this logic to set AML_UART_REG5?


Best regards,
Martin