On Tue, 02 Nov 2021 17:11:20 +0100, Emil Renner Berthing wrote:

Add bindings for the GPIO/pin controller on the JH7100 RISC-V SoC by
StarFive Ltd. This is a test chip for their upcoming JH7110 SoC.

Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
---

@Linus: I'm really struggling to find a good way to describe how pin
muxing works on the JH7100. As you can see I've now resorted to
ascii-art to try to explain it, but please let me know if it's still
unclear.

 .../pinctrl/starfive,jh7100-pinctrl.yaml      | 307 ++++++++++++++++++
 1 file changed, 307 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml

Reviewed-by: Rob Herring <robh@kernel.org>