Hi Jesse,

On Sun, Oct 24, 2021 at 12:40 PM Jesse Taube [off-list ref] wrote:

+#include "clk.h"
+#define ANATOP_BASE_ADDR       0x400d8000

This should be retrieved from the device tree

+       imx_check_clocks(clk, ARRAY_SIZE(clk));
+       clk_data.clks = clk;
+       clk_data.clk_num = ARRAY_SIZE(clk);
+       of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+       clk_set_parent(clk[IMXRT1050_CLK_PLL1_BYPASS], clk[IMXRT1050_CLK_PLL1_REF_SEL]);

The clock parent description could be made via device tree.