The fsl,icc-id property here is used to link the icc node
registered by the imx8mq interconnect driver with the ddrc
device.
Signed-off-by: Abel Vesa <redacted>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 4066b1612655..8ddbeaddf55a 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1552,10 +1552,12 @@ ddrc: memory-controller@3d400000 {
compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
reg = <0x3d400000 0x400000>;
clock-names = "core", "pll", "alt", "apb";
+ fsl,icc-id = <IMX8MQ_ICS_DRAM>;
clocks = <&clk IMX8MQ_CLK_DRAM_CORE>,
<&clk IMX8MQ_DRAM_PLL_OUT>,
<&clk IMX8MQ_CLK_DRAM_ALT>,
<&clk IMX8MQ_CLK_DRAM_APB>;
+ #interconnect-cells = <0>;
};
ddr-pmu@3d800000 {--
2.31.1