On Tue, 3 Aug 2021 at 10:37, Krzysztof Kozlowski
[off-list ref] wrote:
On 03/08/2021 01:06, Sam Protsenko wrote:
(...)
quoted
quoted
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diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h
index f6c3323fc4c5..013c2646863e 100644
--- a/include/linux/serial_s3c.h
+++ b/include/linux/serial_s3c.h
@@ -28,6 +28,15 @@
#define S3C2410_UFSTAT (0x18)
#define S3C2410_UMSTAT (0x1C)
+/* USI Control Register offset */
+#define USI_CON (0xC4)
+/* USI Option Register offset */
+#define USI_OPTION (0xC8)
+/* USI_CON[0] = 0b0: clear USI global software reset (Active High) */
+#define USI_RESET (0<<0)
Just 0x0. I understand you wanted to hint it is a bit field, but the
shift of 0 actually creates more questions.
After some consideration I decided to adhere to existing style and do
something like this (in v2):
8<--------------------------------------------------------------------->8
#define USI_CON (0xC4)
#define USI_OPTION (0xC8)
#define USI_CON_RESET_CLEAR (0<<0)
#define USI_CON_RESET_SET (1<<0)
#define USI_CON_RESET_MASK (1<<0)
#define USI_OPTION_HWACG_CLKREQ_ON (1<<1)
#define USI_OPTION_HWACG_CLKSTOP_ON (1<<2)
#define USI_OPTION_HWACG_MASK (3<<1)
8<--------------------------------------------------------------------->8
The whole reason for those comments was missing public TRM. But in the
end I decided it just looks ugly. Also, this way I can do RMW
operation (discussed above) in more logical way.
Please let me know if code snippets above look good to you.
Please skip the USI_CON_RESET_CLEAR. There is no such pattern in the
code. Clearing bit is an obvious operation and such code is already
everywhere:
val &= ~USI_CON_RESET
(or &= ~USI_RESET_MASK)
Therefore for USI_CON_RESET only:
#define USI_CON_RESET (1<<0)
#define USI_CON_RESET_MASK (1<<0)
Sure, I'll make it so.
Best regards,
Krzysztof