Hello Raviteja,

On 6/3/21 10:03 AM, Raviteja Narayanam wrote:

Hi,

The uart peripheral on Xilinx Versal platform is ARM primecell. Our
environment is 32-bit access type but the ARM primecell uart in pl011
driver has default 16 bit access type. 
(https://github.com/torvalds/linux/blob/master/drivers/tty/serial/amba-pl011.c#L2665
access_32b is false for 'vendor_arm') This is causing asynchronous
abort on our platform when any UART register is written from the
pl011 driver.

Need suggestion on how we can address this issue and if the below
approach is fine.

Check drivers/tty/serial/amba-pl011.c code, there are quite many
controllers with 32-bit access, for instance ZTE UART and SBSA UART.

In other words this case is already well covered in the code, nothing
extraordinary is required or have to be invented here.

As this is platform specific issue, we can have a new device tree
property (memory_access_type), specifying the 32 bit type. In the
probe function, override the behavior (uap->port.iotype) if this
property is present in DT. In this way, we can have support for our
SOC, without breaking any legacy ones.

No, there is totally no need for this kind of a device tree property.

Instead please introduce a new compatible of your controller, just
like it's been done for the SBSA UART controller:

   compatible = "arm,sbsa-uart", "arm,pl011", "arm,primecell";

Then based on a match against your new compatible select a proper
configuration of the device driver, as I've said above similar cases
are already found in the code.

--
Best wishes,
Vladimir