[PATCH AUTOSEL 5.4 08/26] riscv: Fix sifive serial driver
From: Sasha Levin <sashal@kernel.org>
Date: 2021-01-20 02:49:28
Also in:
linux-riscv, lkml, stable
Subsystem:
the rest, tty layer and serial drivers · Maintainers:
Linus Torvalds, Greg Kroah-Hartman, Jiri Slaby
From: Damien Le Moal <redacted> [ Upstream commit 1f1496a923b6ba16679074fe77100e1b53cdb880 ] Setup the port uartclk in sifive_serial_probe() so that the base baud rate is correctly printed during device probe instead of always showing "0". I.e. the probe message is changed from 38000000.serial: ttySIF0 at MMIO 0x38000000 (irq = 1, base_baud = 0) is a SiFive UART v0 to the correct: 38000000.serial: ttySIF0 at MMIO 0x38000000 (irq = 1, base_baud = 115200) is a SiFive UART v0 Signed-off-by: Damien Le Moal <redacted> Reviewed-by: Palmer Dabbelt <redacted> Acked-by: Palmer Dabbelt <redacted> Signed-off-by: Palmer Dabbelt <redacted> Signed-off-by: Sasha Levin <sashal@kernel.org> --- drivers/tty/serial/sifive.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/tty/serial/sifive.c b/drivers/tty/serial/sifive.c
index b4343c6aa6512..6a2dc823ea828 100644
--- a/drivers/tty/serial/sifive.c
+++ b/drivers/tty/serial/sifive.c@@ -973,6 +973,7 @@ static int sifive_serial_probe(struct platform_device *pdev) /* Set up clock divider */ ssp->clkin_rate = clk_get_rate(ssp->clk); ssp->baud_rate = SIFIVE_DEFAULT_BAUD_RATE; + ssp->port.uartclk = ssp->baud_rate * 16; __ssp_update_div(ssp); platform_set_drvdata(pdev, ssp);
--
2.27.0