On Tue, May 09, 2017 at 10:25:40AM +0300, Mika Penttilä wrote:

On 05/09/2017 10:14 AM, Uwe Kleine-König wrote:

quoted

Hello Mika,

On Tue, May 09, 2017 at 07:18:09AM +0300, Mika Penttilä wrote:

quoted

The following commit e61c38d85b7 makes the uarts on i.MX6 nonfunctional (no data transmitted or received). 
With e61c38d85b7 reverted the uarts work ok.

-------------------
commit e61c38d85b7392e033ee03bca46f1d6006156175
Author: Uwe Kleine-König [off-list ref]
Date:   Tue Apr 4 11:18:51 2017 +0200

    serial: imx: setup DCEDTE early and ensure DCD and RI irqs to be off
 
--------------------

are you operating the UART in DTE or DCE mode? Does this affect all
UARTs or only those that are not used in the bootloader?

I am operating in DCE mode. The debug/console uart works ok, but two others don't.

quoted

Looking at the patch I wonder if setting IMX21_UCR3_RXDMUXSEL |
UCR3_ADNIMP is missing for you.

Probably yes, but I can verify this later and get back to you.

can you please test this patch:

diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 33509b4beaec..2182548ff0e1 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c

@@ -2193,9 +2193,14 @@ static int serial_imx_probe(struct platform_device *pdev)
 		 */
 		writel(IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
 		       sport->port.membase + UCR3);
-
 	} else {
+		unsigned long ucr3 = UCR3_DSR;
+
+		if (!is_imx1_uart(sport))
+			ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
+
 		writel(0, sport->port.membase + UFCR);
+		writel(ucr3, sport->port.membase + UCR3);
 	}
 
 	clk_disable_unprepare(sport->clk_ipg);

Best regards
Uwe

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