Hi Wolfram,

On 21.12.2011 01:53, Wolfram Sang wrote:

quoted

Add support for asserting RTS line while TX is in progress. OMAP
hardware doesn't support auto-RS485 mode so we control the line from
software. We use TX_EMPTY_CTL_IT bit in SCR register to generate TX
empty interrupt.

Sorry to bring bad news, but software RS485 is not mainlinable [1].
You can browse linux-serial for RS485 to find more threads about it.

I see. Actually I searched the lists and seen that completely software
solution (using timers) was never merged. This is somewhere in between:
hardware can fire an interrupt exactly after both TX FIFO and shift
register are emptied so it's only the interrupt latency that affects the
timing.

Thanks for your reply anyway. We will have to maintain this patch in our
tree then.

Regards, Ilya.