[PATCH v4 03/16] scsi: ufs: ufs-exynos: change pclk available max value
From: Chanho Park <hidden>
Date: 2021-10-07 08:12:11
Also in:
linux-samsung-soc
Subsystem:
scsi subsystem, the rest · Maintainers:
"James E.J. Bottomley", "Martin K. Petersen", Linus Torvalds
To support 167MHz PCLK, we need to adjust the maximum value. Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Reviewed-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Chanho Park <redacted> --- drivers/scsi/ufs/ufs-exynos.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
index dadf4fd10dd8..0a31f77a5f48 100644
--- a/drivers/scsi/ufs/ufs-exynos.h
+++ b/drivers/scsi/ufs/ufs-exynos.h@@ -99,7 +99,7 @@ struct exynos_ufs; #define PA_HIBERN8TIME_VAL 0x20 #define PCLK_AVAIL_MIN 70000000 -#define PCLK_AVAIL_MAX 133000000 +#define PCLK_AVAIL_MAX 167000000 struct exynos_ufs_uic_attr { /* TX Attributes */
--
2.33.0