Thread (25 messages) 25 messages, 2 authors, 2021-07-29
STALE1819d REVIEWED: 6 (6M)

[PATCH v2 03/15] scsi: ufs: ufs-exynos: change pclk available max value

From: Chanho Park <hidden>
Date: 2021-07-14 07:12:11
Also in: linux-samsung-soc
Subsystem: scsi subsystem, the rest · Maintainers: "James E.J. Bottomley", "Martin K. Petersen", Linus Torvalds

To support 167MHz PCLK, we need to adjust the maximum value.

Signed-off-by: Chanho Park <redacted>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
---
 drivers/scsi/ufs/ufs-exynos.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/scsi/ufs/ufs-exynos.h b/drivers/scsi/ufs/ufs-exynos.h
index 67505fe32ebf..475a5adf0f8b 100644
--- a/drivers/scsi/ufs/ufs-exynos.h
+++ b/drivers/scsi/ufs/ufs-exynos.h
@@ -99,7 +99,7 @@ struct exynos_ufs;
 #define PA_HIBERN8TIME_VAL	0x20
 
 #define PCLK_AVAIL_MIN	70000000
-#define PCLK_AVAIL_MAX	133000000
+#define PCLK_AVAIL_MAX	167000000
 
 struct exynos_ufs_uic_attr {
 	/* TX Attributes */
-- 
2.32.0
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