[PATCH v5 14/17] rtc: rzn1: use FIELD_PREP/FIELD_GET and GENMASK for register access
COLD41d
REVIEWED: 14 (14M)
From: Prabhakar <prabhakar.csengg@gmail.com>
Date: 2026-08-21 13:58:00
Also in:
linux-devicetree, linux-renesas-soc, lkml
Subsystem:
real time clock (rtc) subsystem, renesas rz/n1 rtc controller driver, the rest · Maintainers:
Alexandre Belloni, Miquel Raynal, Linus Torvalds
Revision v5 of 3 in this series; 2 review trailers.
Revisions (3)
- v4 [diff vs current]
- v5 current
- v6 [diff vs current]
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Replace open-coded shift and mask operations with the bitfield API. Note that the weekday field is changed from an explicit 0x0f mask to an 8-bit field definition, matching the hardware manual. This does not change behaviour, as valid weekday values cannot exceed 7. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- v4->v5: - Added Tested-by tag from Wolfram. v3->v4: - Added RB tag from Wolfram v2->v3: - No changes. v1->v2: - Made use of RZN1_RTC_SUBU_RTCA0FX mask for SUBU register access instead of 0x3F. --- drivers/rtc/rtc-rzn1.c | 50 +++++++++++++++++++++++------------------- 1 file changed, 28 insertions(+), 22 deletions(-)
diff --git a/drivers/rtc/rtc-rzn1.c b/drivers/rtc/rtc-rzn1.c
index ea3906d1f868..8b68a5ad19c0 100644
--- a/drivers/rtc/rtc-rzn1.c
+++ b/drivers/rtc/rtc-rzn1.c@@ -12,6 +12,8 @@ */ #include <linux/bcd.h> +#include <linux/bitfield.h> +#include <linux/bits.h> #include <linux/clk.h> #include <linux/init.h> #include <linux/iopoll.h>
@@ -38,14 +40,18 @@ #define RZN1_RTC_CTL2_STOPPED (RZN1_RTC_CTL2_WAIT | RZN1_RTC_CTL2_WST) #define RZN1_RTC_TIME 0x30 -#define RZN1_RTC_TIME_MIN_SHIFT 8 -#define RZN1_RTC_TIME_HOUR_SHIFT 16 +#define RZN1_RTC_TIME_SEC GENMASK(7, 0) +#define RZN1_RTC_TIME_MIN GENMASK(15, 8) +#define RZN1_RTC_TIME_HOUR GENMASK(23, 16) + #define RZN1_RTC_CAL 0x34 -#define RZN1_RTC_CAL_DAY_SHIFT 8 -#define RZN1_RTC_CAL_MON_SHIFT 16 -#define RZN1_RTC_CAL_YEAR_SHIFT 24 +#define RZN1_RTC_CAL_WDAY GENMASK(7, 0) +#define RZN1_RTC_CAL_DAY GENMASK(15, 8) +#define RZN1_RTC_CAL_MON GENMASK(23, 16) +#define RZN1_RTC_CAL_YEAR GENMASK(31, 24) #define RZN1_RTC_SUBU 0x38 +#define RZN1_RTC_SUBU_RTCA0FX GENMASK(5, 0) #define RZN1_RTC_SUBU_DEV BIT(7) #define RZN1_RTC_SUBU_DECR BIT(6)
@@ -77,15 +83,15 @@ static void rzn1_rtc_get_time_snapshot(struct rzn1_rtc *rtc, struct rtc_time *tm u32 val; val = readl(rtc->base + RZN1_RTC_TIMEC); - tm->tm_sec = bcd2bin(val); - tm->tm_min = bcd2bin(val >> RZN1_RTC_TIME_MIN_SHIFT); - tm->tm_hour = bcd2bin(val >> RZN1_RTC_TIME_HOUR_SHIFT); + tm->tm_sec = bcd2bin(FIELD_GET(RZN1_RTC_TIME_SEC, val)); + tm->tm_min = bcd2bin(FIELD_GET(RZN1_RTC_TIME_MIN, val)); + tm->tm_hour = bcd2bin(FIELD_GET(RZN1_RTC_TIME_HOUR, val)); val = readl(rtc->base + RZN1_RTC_CALC); - tm->tm_wday = val & 0x0f; - tm->tm_mday = bcd2bin(val >> RZN1_RTC_CAL_DAY_SHIFT); - tm->tm_mon = bcd2bin(val >> RZN1_RTC_CAL_MON_SHIFT) - 1; - tm->tm_year = bcd2bin(val >> RZN1_RTC_CAL_YEAR_SHIFT) + 100; + tm->tm_wday = FIELD_GET(RZN1_RTC_CAL_WDAY, val); + tm->tm_mday = bcd2bin(FIELD_GET(RZN1_RTC_CAL_DAY, val)); + tm->tm_mon = bcd2bin(FIELD_GET(RZN1_RTC_CAL_MON, val)) - 1; + tm->tm_year = bcd2bin(FIELD_GET(RZN1_RTC_CAL_YEAR, val)) + 100; } static int rzn1_rtc_read_time(struct device *dev, struct rtc_time *tm)
@@ -128,15 +134,15 @@ static int rzn1_rtc_set_time(struct device *dev, struct rtc_time *tm) return ret; } - val = bin2bcd(tm->tm_sec); - val |= bin2bcd(tm->tm_min) << RZN1_RTC_TIME_MIN_SHIFT; - val |= bin2bcd(tm->tm_hour) << RZN1_RTC_TIME_HOUR_SHIFT; + val = FIELD_PREP(RZN1_RTC_TIME_SEC, bin2bcd(tm->tm_sec)) | + FIELD_PREP(RZN1_RTC_TIME_MIN, bin2bcd(tm->tm_min)) | + FIELD_PREP(RZN1_RTC_TIME_HOUR, bin2bcd(tm->tm_hour)); writel(val, rtc->base + RZN1_RTC_TIME); - val = tm->tm_wday; - val |= bin2bcd(tm->tm_mday) << RZN1_RTC_CAL_DAY_SHIFT; - val |= bin2bcd(tm->tm_mon + 1) << RZN1_RTC_CAL_MON_SHIFT; - val |= bin2bcd(tm->tm_year - 100) << RZN1_RTC_CAL_YEAR_SHIFT; + val = FIELD_PREP(RZN1_RTC_CAL_WDAY, tm->tm_wday) | + FIELD_PREP(RZN1_RTC_CAL_DAY, bin2bcd(tm->tm_mday)) | + FIELD_PREP(RZN1_RTC_CAL_MON, bin2bcd(tm->tm_mon + 1)) | + FIELD_PREP(RZN1_RTC_CAL_YEAR, bin2bcd(tm->tm_year - 100)); writel(val, rtc->base + RZN1_RTC_CAL); writel(0, rtc->base + RZN1_RTC_CTL2);
@@ -307,12 +313,12 @@ static int rzn1_rtc_read_offset(struct device *dev, long *offset) val = readl(rtc->base + RZN1_RTC_SUBU); ppb_per_step = val & RZN1_RTC_SUBU_DEV ? 1017 : 3051; subtract = val & RZN1_RTC_SUBU_DECR; - val &= 0x3F; + val = FIELD_GET(RZN1_RTC_SUBU_RTCA0FX, val); if (!val) *offset = 0; else if (subtract) - *offset = -(((~val) & 0x3F) + 1) * ppb_per_step; + *offset = -(((~val) & RZN1_RTC_SUBU_RTCA0FX) + 1) * ppb_per_step; else *offset = (val - 1) * ppb_per_step;
@@ -354,7 +360,7 @@ static int rzn1_rtc_set_offset(struct device *dev, long offset) subu |= steps + 1; } else { subu |= RZN1_RTC_SUBU_DECR; - subu |= (~(-steps - 1)) & 0x3F; + subu |= (~(-steps - 1)) & RZN1_RTC_SUBU_RTCA0FX; } ret = readl_poll_timeout(rtc->base + RZN1_RTC_CTL2, ctl2,
--
2.43.0