Re: [RFC 3/5] dma-mapping: Enable global non-coherent pool support for RISC-V
From: Rob Herring <robh+dt@kernel.org>
Date: 2021-07-25 22:29:28
Also in:
linux-devicetree, linux-iommu, lkml
From: Rob Herring <robh+dt@kernel.org>
Date: 2021-07-25 22:29:28
Also in:
linux-devicetree, linux-iommu, lkml
On Fri, Jul 23, 2021 at 3:40 PM Atish Patra [off-list ref] wrote:
Currently, linux,dma-default is used to reserve a global non-coherent pool to allocate memory for dma operations. This can be useful for RISC-V as well as the ISA specification doesn't specify a method to modify PMA attributes or page table entries to define non-cacheable area yet. A non-cacheable memory window is an alternate options for vendors to support non-coherent devices. "dma-ranges" must be used in conjunction with "linux,dma-default" property to define one or more mappings between device and cpu accesible memory regions.
'dma-ranges' applies to buses. And, well, maybe devices when the bus is not well defined. It is not a reserved-memory property. Rob _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv