Thread (6 messages) 6 messages, 2 authors, 2021-07-13

Re: [PATCH 1/2] riscv: dts: microchip: Drop "clock-frequency" property of cpu nodes

From: <Conor.Dooley@microchip.com>
Date: 2021-07-13 15:29:12
Also in: lkml

On 16/06/2021 07:02, Bin Meng wrote:
quoted hunk ↗ jump to hunk
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From: Bin Meng <redacted>

The "clock-frequency" property of cpu nodes isn't required. Drop it.

Signed-off-by: Bin Meng <redacted>
---

  arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 -----
  1 file changed, 5 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index b9819570a7d1..ee54878b3f89 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -17,7 +17,6 @@ cpus {
                 #size-cells = <0>;

                 cpu@0 {
-                       clock-frequency = <0>;
                         compatible = "sifive,e51", "sifive,rocket0", "riscv";
                         device_type = "cpu";
                         i-cache-block-size = <64>;
@@ -35,7 +34,6 @@ cpu0_intc: interrupt-controller {
                 };

                 cpu@1 {
-                       clock-frequency = <0>;
                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
                         d-cache-block-size = <64>;
                         d-cache-sets = <64>;
@@ -62,7 +60,6 @@ cpu1_intc: interrupt-controller {
                 };

                 cpu@2 {
-                       clock-frequency = <0>;
                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
                         d-cache-block-size = <64>;
                         d-cache-sets = <64>;
@@ -89,7 +86,6 @@ cpu2_intc: interrupt-controller {
                 };

                 cpu@3 {
-                       clock-frequency = <0>;
                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
                         d-cache-block-size = <64>;
                         d-cache-sets = <64>;
@@ -116,7 +112,6 @@ cpu3_intc: interrupt-controller {
                 };

                 cpu@4 {
-                       clock-frequency = <0>;
                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
                         d-cache-block-size = <64>;
                         d-cache-sets = <64>;
--
2.25.1
Reviewed-by: conor dooley<conor.dooley@microchip.com>
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