Re: [PATCH v16 03/16] dt-bindings: update risc-v cpu properties
From: Rob Herring <robh@kernel.org>
Date: 2021-02-05 19:50:19
Also in:
linux-devicetree
On Fri, 05 Feb 2021 15:58:14 +0900, Damien Le Moal wrote:
The Canaan Kendryte K210 SoC CPU cores are based on a rocket chip version using a draft verion of the RISC-V ISA specifications. To avoid any confusion with CPU cores using stable specifications, add the compatible string "canaan,k210" for this SoC CPU cores. Also add the "riscv,none" value to the mmu-type property to allow a DT to indicate that the CPU being described does not have an MMU or that it has an MMU that is not usable (which is the case for the K210 SoC). Cc: Paul Walmsley <redacted> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Signed-off-by: Damien Le Moal <redacted> Reviewed-by: Atish Patra <redacted> Reviewed-by: Anup Patel <anup@brainfault.org> --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++ 1 file changed, 2 insertions(+)
Acked-by: Rob Herring <robh@kernel.org> _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv