On Wed, Jun 09, 2021 at 02:52:41PM +0200, Christoph Hellwig wrote:

On Wed, Jun 09, 2021 at 02:05:03PM +0300, Leon Romanovsky wrote:

quoted

From: Avihai Horon <redacted>

Relaxed Ordering is a capability that can only benefit users that support
it. All kernel ULPs should support Relaxed Ordering, as they are designed
to read data only after observing the CQE and use the DMA API correctly.

Hence, implicitly enable Relaxed Ordering by default for kernel ULPs.

Signed-off-by: Avihai Horon <redacted>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
---
Changelog:
v2:
 * Dropped IB/core patch and set RO implicitly in mlx5 exactly like in
   eth side of mlx5 driver.

This looks great in terms of code changes.  But can we please also add a
patch to document that PCIe relaxed ordering is fine for kernel ULP usage
somewhere?

Sure, did you have in mind some concrete place? Or will new file in the
Documentation/infiniband/ folder be good enough too?

Thanks