Re: [PATCH v10 08/22] IB/hns: Add icm support

On Wed, Jun 22, 2016 at 11:53:17AM +0800, Wei Hu (Xavier) wrote:

- netdev, lkml and Dave - it is unrelated to netdev and there is no
  need to SPAM them.

It will be great if next revision will have smaller list of TO/CC
participants than it has now.

On 2016/6/21 19:55, Leon Romanovsky wrote:

quoted

On Tue, Jun 21, 2016 at 12:37:39PM +0800, Wei Hu (Xavier) wrote:

quoted

On 2016/6/20 21:04, Leon Romanovsky wrote:

quoted

On Mon, Jun 20, 2016 at 05:48:15PM +0800, Wei Hu (Xavier) wrote:

quoted

On 2016/6/20 17:27, Leon Romanovsky wrote:

quoted

On Mon, Jun 20, 2016 at 03:49:24PM +0800, Wei Hu (Xavier) wrote:

quoted

On 2016/6/20 14:06, Leon Romanovsky wrote:

quoted

On Mon, Jun 20, 2016 at 12:37:40PM +0800, Wei Hu (Xavier) wrote:

quoted

On 2016/6/17 17:58, Leon Romanovsky wrote:

quoted

On Thu, Jun 16, 2016 at 10:35:16PM +0800, Lijun Ou wrote:

quoted

This patch mainly added icm support for RoCE. It initializes icm
which managers the relative memory blocks for RoCE. The data
structures of RoCE will be located in it. For example, CQ table,
QP table and MTPT table so on.

Signed-off-by: Wei Hu <redacted>
Signed-off-by: Nenglong Zhao <zhaonenglong-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
Signed-off-by: Lijun Ou <redacted>
---

<...>

quoted

+

Another question which you didn't answer [1].

"I wonder if you have the same needs for ICM as it is in mlx4 device.
Do you have firmware?"

[1] http://marc.info/?l=linux-rdma&m=146545553104913&w=2

Hi, Leon
    Now we haven't firmware.
    But hardware still need memory for QPC\CQC\MTPT\mtt etc.

ICM stands for InfiniHost (Interconnect) Context Memory is a specific
memory place to share between host <-> FW and host <-> HW if HW is
aware of specific structures.

I assume that in your case, it is enough to allocate memory region and
supply it to HW. Am I right?

For Our hardware,
1. ICM has a memory management method, It's very good for QPC\CQC\MTPT\mtt
etc. we need it.

You need special HW to leverage its. AFAIK it is Mellanox specific.

For our hardware, we use ICM to memory management, the memory shared with
host and HW.
QPC\CQC\MTPT\mtt has specific memory requirement.
QPC\CQC\MTPT need continuous memory. we use ICM to management the block of
memory. It's very good！

I wasn't convinced why do you need to copy whole ICM logic which is
specific to Mellanox. Your requirements can be implemented by standard CMA
and/or DMA.

Hi, Leon

In hip06 soc,
Hardware need multiple memory blocks for QPC\CQC\MTPT, every block has
continuous memory xxKbyte (like 128Kbyte),
We need to configure the first address of 128Kbyte to hardware.

For example:
//------------------------------------------------------------------------
example 1:
In create qp,
1. If the xx Kbyte memory that include QPC related with qpn, has not been
allocated, do step 2.
   else do step 3.
2. dma_alloc xx Kbyte memory for QPC,  and configure the first address of xx
Kbyte to hardware.
3. find the QPC memory in xx Kbyte, get the dma_addr.
4. send mailbox command to hardware to create QP.

In step 2, we call xx_table_get function as below to perform logic.
int hns_roce_table_get(struct hns_roce_dev *hr_dev,
               struct hns_roce_icm_table *table, unsigned long obj)
{
    <snip>
    //dma_alloc_coherent 128Kbyte memory
    hns_roce_alloc_icm(hr_dev,
                  HNS_ROCE_TABLE_CHUNK_SIZE >> PAGE_SHIFT, xxxx);
    <snip>
    /*configure the first address of xx Kbyte to hardware*/
    hns_roce_map_icm(hr_dev, table, obj);
    <snip>
}

In step 3, we call xx_table_find function to perform logic.
void *hns_roce_table_find(struct hns_roce_icm_table *table, unsigned long
obj,
              dma_addr_t *dma_handle);


example 2:
In modify qp:
1. find the QPC memory,  get the virtual addr.
2. modify the fields of QPC.
3. send mailbox command to hardware to modify QP.

In step 1,  we call xx_table_find function to perform logic.
//--------------------------------------------------------------------------


so, now we haven't a firmware, but ICM algorithm still suitable for hip06
soc perfectly.

Sure it works and you have billion other solutions in kernel which will
work too. The thing is to chose simplest possible solution and ICM is
overkill for the goal you are trying to achieve. ICM designed in mind
that this memory is owned by HW, requested by HCA and can shrink/grow
as a response to this request.

Thanks